HD64F2168 Datasheet, PDF (518/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

[8] Wait for one clock pulse
SCL
(master output)
8
SDA
Bit 0
(slave output)
Data 2
[3]
SDA
(master output)
IRIC
9
1
2
3
4
5
6
7
8
9
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
[3]
Data 3
[12]
[12]
A
A
Stop condition generation
IRTR
[4] IRTR=0
[4] IRTR=1
[13] IRTR=0 [13] IRTR=1
ICDR
Data 1
Data 2
Data 3
User processing
[6] IRIC clear
(to end wait
insertion)
[11] IRIC clear
[10] ICDR read (Data 2)
[9] Set TRS=1
[7] Set ACKB=1
[15] WAIT cleared to 0,
IRIC clear
[14] IRIC clear
(to end wait
insertion)
[17] Stop condition issuance
[16] ICDR read
(Data 3)
Figure 15.16 Stop Condition Issuance Timing Example in Master Receive Mode
(MLS = ACKB = 0, WAIT = 1)
15.4.5 Slave Receive Operation
In I²C bus format slave receive mode, the master device outputs the transmit clock and transmit
data, and the slave device returns an acknowledge signal.
The slave device operates as the device specified by the master device when the slave address in
the first frame following the start condition that is issued by the master device matches its own
address.
Rev. 3.00, 03/04, page 478 of 830