HD64F2168 Datasheet, PDF (372/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

12.9.3 Conflict between TCOR Write and Compare-Match
If a compare-match occurs during the T₂ state of a TCOR write cycle as shown in figure 12.15, the
TCOR write takes priority and the compare-match signal is disabled. With TMR_X, a TICR input
capture conflicts with a compare-match in the same way as with a write to TCORC. In this case
also, the input capture takes priority and the compare-match signal is disabled.
TCOR write cycle by CPU
T1
T2
φ
Address
TCOR address
Internal write signal
TCNT
N
N+1
TCOR
N
M
Compare-match signal
TCOR write data
Disabled
Figure 12.15 Conflict between TCOR Write and Compare-Match
Rev. 3.00, 03/04, page 332 of 830