HD64F2168 Datasheet, PDF (270/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

PAnDDR
Pin function
[Legend]
n = 7 to 2
m = 15 to 10
0
PAn input pins
KINm input pin/EVENTn input pins
1
PAn output pins
• PA1/KIN9/EVENT1/SSE2I
The function of port A pins is switched as shown below according to the combination of the
SSE bit in SEMR of SCI_2, the C/A bit in SMR, the CKE1 bit in SCR, and the PA1DDR bit.
When the KMIM9 bit in KMIMRA of the interrupt controller is cleared to 0, this pin can be
used as the KIN9 input pin. To use this pin as the KIN9 input pin, clear the PA1DDR bit to 0.
When this pin is used as the EVENT1 input pin according to bits ECSB3 to ECSB0 in ECCR
of the data transfer controller settings, clear the PA1DDR bit to 0. Though this pin has been set
to the EVENT1 input pin, to use as the PA1 output pin, set the PA1DDR bit to1.
SSE
C/A
CKE1
PA1DDR
Pin function
0


0
PA1 input pin
KIN9 input pin
/EVENT1 input pin
1
PA1 output pin
1
1
1

SSE2I input pin
• PA0/KIN8/EVENT0/SSE0I
The function of port A pins is switched as shown below according to the combination of the
SSE bit in SEMR of SCI_0, the C/A bit in SMR, the CKE1 bit in SCR, and the PA0DDR bit.
When the KMIM8 bit in KMIMRA of the interrupt controller is cleared to 0, this pin can be
used as the KIN8 input pin. To use this pin as the KIN8 input pin, clear the PA0DDR bit to 0.
When this pin is used as the EVENT0 input pin according to bits ECSB3 to ECSB0 in ECCR
of the data transfer controller settings, clear the PA0DDR bit to 0. Though this pin has been set
to the EVENT0 input pin, to use as the PA0 output pin, set the PA0DDR bit to1.
Rev. 3.00, 03/04, page 230 of 830