HD64F2168 Datasheet, PDF (427/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

14.4.6 Serial Data Transmission (Asynchronous Mode)
Figure 14.9 shows an example of the operation for transmission in asynchronous mode. In
transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SSR, and if it is cleared to 0, recognizes that data has been
written to TDR, and transfers the data from TDR to TSR.
2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmission. If the TIE bit in SCR is set to 1 at this time, a transmit data empty interrupt
request (TXI) is generated. Because the TXI interrupt routine writes the next transmit data to
TDR before transmission of the current transmit data has finished, continuous transmission can
be enabled.
3. Data is sent from the TxD pin in the following order: start bit, transmit data, parity bit or
multiprocessor bit (may be omitted depending on the format), and stop bit.
4. The SCI checks the TDRE flag at the timing for sending the stop bit.
5. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then
serial transmission of the next frame is started.
6. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the “mark
state” is entered in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI
interrupt request is generated.
Figure 14.10 shows a sample flowchart for transmission in asynchronous mode.
Start
Data
Parity Stop Start
Data
Parity Stop
1 bit
bit bit bit
bit bit 1
0 D0 D1
D7 0/1 1 0 D0 D1
D7 0/1
1
Idle state
(mark state)
TDRE
TEND
TXI interrupt
Data written to TDR and TXI interrupt
request generated TDRE flag cleared to 0 in request generated
TXI interrupt service routine
TEI interrupt
request generated
1 frame
Figure 14.9 Example of Operation in Transmission in Asynchronous Mode (Example with
8-Bit Data, Parity, One Stop Bit)
Rev. 3.00, 03/04, page 387 of 830