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HD64F2168 Datasheet, PDF (550/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer | |||
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16.3 Register Descriptions
The LPC registers are listed in the following. Though this LSI accesses these registers as a slave,
some of them can be accessed from the host. For details, see each register description.
⢠Host interface control register 0 (HICR0)
⢠Host interface control register 1 (HICR1)
⢠Host interface control register 2 (HICR2)
⢠Host interface control register 3 (HICR3)
⢠Host interface control register 4 (HICR4)
⢠LPC channel 3 Address register H, L (LADR3H, LADR3L)
⢠LPC channel 1, 2 address register H, L (LADR12H, LADR12L)
⢠Input data register 1 (IDR1)
⢠Input data register 2 (IDR2)
⢠Input data register 3 (IDR3)
⢠Output data register 1 (ODR1)
⢠Output data register 2 (ODR2)
⢠Output data register 3 (ODR3)
⢠Bidirectional data registers 0 to 15 (TWR0 to TWR15)
⢠Status register 1 (STR1)
⢠Status register 2 (STR2)
⢠Status register 3 (STR3)
⢠SERIRQ control register 0 (SIRQCR0)
⢠SERIRQ control register 1 (SIRQCR1)
⢠SERIRQ control register 2 (SIRQCR2)
⢠Host interface select register (HISEL)
SMIC mode:
The following registers are required when SMIC mode is used.
⢠SMIC flag register (SMICFLG)
⢠SMIC control status register (SMICCSR)
⢠SMIC data register (SMICDTR)
⢠SMIC interrupt register 0 (SMICIR0)
⢠SMIC interrupt register 1 (SMICIR1)
Rev. 3.00, 03/04, page 510 of 830
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