HD64F2168 Datasheet, PDF (36/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Table 5.8
Table 5.9
Number of States in Interrupt Handling Routine Execution Status ........................ 96
Interrupt Source Selection and Clearing Control .................................................... 98
Section 6 Bus Controller (BSC)
Table 6.1 Pin Configuration.................................................................................................. 104
Table 6.2 Address Ranges and External Address Spaces ..................................................... 113
Table 6.3 Bit Settings and Bus Specifications of Basic Bus Interface.................................. 114
Table 6.4 Bus Specifications for Basic Extended Area/Basic Bus Interface ........................ 115
Table 6.5 Bus Specifications for 256-kbyte Extended Area/Basic Bus Interface................. 116
Table 6.6 Bus Specifications for CP Extended Area (Basic Mode)/Basic Bus Interface ..... 117
Table 6.7 Address-Data Multiplex Address Spaces.............................................................. 119
Table 6.8 Bit Settings and Bus Specifications of Basic Bus Interface.................................. 120
Table 6.9 Bus Specifications for IOS Extended Area/Multiplex Bus Interface
(Address Cycle) .................................................................................................... 120
Table 6.10 Bus Specifications for IOS Extended Area/Multiplex Bus Interface
(Data Cycle) ......................................................................................................... 120
Table 6.11 Bus Specifications for 256-kbyte Extended Area/Multiplex Bus Interface
(Address Cycle).................................................................................................... 121
Table 6.12 Bus Specifications for 256-kbyte Extended Area/Multiplex Bus Interface
(Data Cycle) ......................................................................................................... 121
Table 6.13 Bus Specifications for CP Extended Area/Multiplex Bus Interface
(Address Cycle).................................................................................................... 121
Table 6.14 Bus Specifications for CP Extended Area/Multiplex Bus Interface
(Data Cycle) ......................................................................................................... 122
Table 6.15 Address Range for IOS Signal Output.................................................................. 123
Table 6.16 Data Buses Used and Valid Strobes...................................................................... 126
Table 6.17 Pin States in Idle Cycle......................................................................................... 147
Section 7 Data Transfer Controller (DTC)
Table 7.1 Correspondence between Interrupt Sources and DTCER ..................................... 155
Table 7.2 DTC Event Counter Conditions............................................................................ 159
Table 7.3 Flag Status/Address Code..................................................................................... 160
Table 7.4 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs .............. 163
Table 7.4 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs (cont) .... 164
Table 7.5 Register Functions in Normal Mode..................................................................... 166
Table 7.6 Register Functions in Repeat Mode...................................................................... 167
Table 7.7 Register Functions in Block Transfer Mode ......................................................... 168
Table 7.8 DTC Execution Status .......................................................................................... 171
Table 7.9 Number of States Required for Each Execution Status ........................................ 172
Section 8 I/O Ports
Table 8.1 Port Functions....................................................................................................... 177
Table 8.1 Port Functions (cont) ............................................................................................ 178
Table 8.1 Port Functions (cont) ............................................................................................ 179
Rev. 3.00, 03/04, page xxxvi of xl