HD64F2168 Datasheet, PDF (780/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

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peripheral module clock
Bus master clock
Medium-speed mode
Internal address bus
SBYCR
SBYCR
Internal write signal
Figure 23.2 Medium-Speed Mode Timing
23.4 Sleep Mode
The CPU makes a transition to sleep mode if the SLEEP instruction is executed when the SSBY
bit in SBYCR is cleared to 0 and the LSON bit in LPWRCR is cleared to 0. In sleep mode, CPU
operation stops but the peripheral modules do not stop. The contents of the CPU’s internal
registers are retained.
Sleep mode is exited by any interrupt, the RES pin, or the STBY pin.
When an interrupt occurs, sleep mode is exited and interrupt exception handling starts. Sleep mode
is not exited if the interrupt is disabled, or interrupts other than NMI are masked by the CPU.
Setting the RES pin level low cancels sleep mode and selects the reset state. After the oscillation
settling time has passed, driving the RES pin high causes the CPU to start reset exception
handling.
When the STBY pin level is driven low, a transition is made to hardware standby mode.
Rev. 3.00, 03/04, page 740 of 830