HD64F2168 Datasheet, PDF (547/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 16 LPC Interface (LPC)
This LSI has an on-chip LPC interface.
The LPC performs serial transfer of cycle type, address, and data, synchronized with the 33 MHz
PCI clock. It uses four signal lines for address/data, and one for host interrupt requests. The LPC
interface operates as a slave and supports only I/O read cycle and I/O write cycle transfer.
It is also provided with power-down functions that can control the PCI clock and shut down the
LPC interface.
16.1 Features
• Supports LPC interface I/O read cycles and I/O write cycles
Uses four signal lines (LAD3 to LAD0) to transfer the cycle type, address, and data.
Uses three control signals: clock (LCLK), reset (LRESET), and frame (LFRAME).
• Has three register sets comprising data and status registers
The basic register set comprises three bytes: an input register (IDR), output register (ODR),
and status register (STR).
Channels 1 to 3 have fixed I/O addresses of H'0000 to H'FFFF, respectively.
A fast A20 gate function is also provided.
Sixteen bidirectional data register bytes can be manipulated in addition to the basic register set.
• Supports SERIRQ
Host interrupt requests are transferred serially on a single signal line (SERIRQ).
On channel 1, HIRQ1 and HIRQ12 can be generated.
On channels 2 and 3, SMI, HIRQ6, and HIRQ9 to HIRQ11 can be generated.
Operation can be switched between quiet mode and continuous mode.
The CLKRUN signal can be manipulated to restart the PCI clock (LCLK).
• Power-down functions, interrupts, etc.
The LPC module can be shut down by inputting the LPCPD signal.
Three pins, PME, LSMI, and LSCI, are provided for general input/output.
• Supports version 1.5 of the Intelligent Platform Management Interface (IPMI)
Channel 3 supports the SMIC interface, KCS interface, and BT interface.
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