HD64F2168 Datasheet, PDF (138/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Operation Order: If the same interrupt is selected as a DTC activation source and a CPU
interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception
handling.
Table 5.9 summarizes interrupt source selection and interrupt source clearing control according to
the settings of the DTCE bit of DTCERA to DTCERE in the DTC and the DISEL bit of MRB in
the DTC.
Table 5.9 Interrupt Source Selection and Clearing Control
Settings
DTC
Interrupt Source Selection/Clearing Control
DTCE
DISEL
DTC
CPU
0
*
×
∆
1
0
∆
×
1
∆
[Legend]
∆:
The relevant interrupt is used. Interrupt source clearing is performed.
(The CPU should clear the source flag in the interrupt handling routine.)
:
The relevant interrupt is used. The interrupt source is not cleared.
×:
The relevant interrupt cannot be used.
*:
Don’t care
Rev. 3.00, 03/04, page 98 of 830