HD64F2168 Datasheet, PDF (499/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

15.3.8 I²C Bus Extended Control Register (ICXR)
ICXR enables or disables the I²C bus interface interrupt generation and continuous receive
operation, and indicates the status of receive/transmit operations.
Initial
Bit
Bit Name Value R/W Description
7
STOPIM 0
R/W Stop Condition Interrupt Source Mask
Enables or disables the interrupt generation when the stop
condition is detected in slave mode.
0: Enables IRIC flag setting and interrupt generation when
the stop condition is detected (STOP = 1 or ESTP = 1)
in slave mode.
1: Disables IRIC flag setting and interrupt generation when
the stop condition is detected.
6
HNDS
0
R/W Handshake Receive Operation Select
Enables or disables continuous receive operation in
receive mode.
0: Enables continuous receive operation
1: Disables continuous receive operation
When the HNDS bit is cleared to 0, receive operation is
performed continuously after data has been received
successfully while ICDRF flag is 0.
When the HNDS bit is set to 1, SCL is fixed to the low
level after data has been received successfully while
ICDRF flag is 0; thus disabling the next data to be
transferred. The bus line is released and next receive
operation is enabled by reading the receive data in ICDR.
Rev. 3.00, 03/04, page 459 of 830