HD64F2168 Datasheet, PDF (314/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Base cycle
No. 0
1 conversion cycle
Base cycle
No. 1
Base cycle
No. 63
Base pulse
High width: 2/256 × (T)
Base pulse
2/256 × (T)
Additional pulse output location
Additional pulse
1/256 × (T)
Figure 10.6 Output Waveform when DADR = H'0207 (OS = 1)
However, when CFS = 0 (base cycle = resolution (T) × 64), the duty cycle of the base pulse is
determined by the upper six bits and the locations of the additional pulses by the subsequent eight
bits with a method similar to as above.
Rev. 3.00, 03/04, page 274 of 830