HD64F2168 Datasheet, PDF (535/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

15.6 Usage Notes
1. In master mode, if an instruction to generate a start condition is immediately followed by an
instruction to generate a stop condition, neither condition will be output correctly. To output
consecutive start and stop conditions*, after issuing the instruction that generates the start
condition, read the relevant DR registers of I²C bus output pins, check that SCL and SDA are
both low. If the ICE bit is set to 1, pin state can be monitored by reading DR register. Then
issue the instruction that generates the stop condition. Note that SCL may not yet have gone
low when BBSY is cleared to 0.
Note: * An illegal procedure in the I²C bus specification.
2. Either of the following two conditions will start the next transfer. Pay attention to these
conditions when accessing to ICDR.
 Write to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from ICDRT to
ICDRS)
 Read from ICDR when ICE = 1 and TRS = 0 (including automatic transfer from ICDRS to
ICDRR)
3. Table 15.11 shows the timing of SCL and SDA outputs in synchronization with the internal
clock. Timings on the bus are determined by the rise and fall times of signals affected by the
bus load capacitance, series resistance, and parallel resistance.
Table 15.11 I²C Bus Timing (SCL and SDA Outputs)
Item
Symbol Output Timing
SCL output cycle time
SCL output high pulse width
SCL output low pulse width
SDA output bus free time
Start condition output hold time
Retransmission start condition output
setup time
t
SCLO
t
SCLHO
t_SCLLO
t_BUFO
t_STAHO
t_STASO
28t to 512t
cyc
cyc
0.5t
SCLO
0.5t_SCLO
0.5t_SCLO – 1t_cyc
0.5t_SCLO – 1t_cyc
1t_SCLO
Stop condition output setup time
t
STOSO
0.5t + 2t
SCLO
cyc
Data output setup time (master)
t
SDASO
1t – 3t
SCLLO
cyc
Data output setup time (slave)
1t
SCLLO
–
(6t
cyc
or
12t_cyc*)
Data output hold time
t
SDAHO
3t
cyc
Note: * 6t_cyc when IICXn is 0, 12t_cyc when IICXn is 1 (n = 0 to 5).
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
See figure
25.30
(reference)
Rev. 3.00, 03/04, page 495 of 830