HD64F2168 Datasheet, PDF (761/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 22 Clock Pulse Generator
This LSI incorporates a clock pulse generator which generates the system clock (φ), internal clock,
bus master clock, and subclock (φSUB). The clock pulse generator consists of an oscillator, PLL
multiplier circuit, system clock select circuit, medium-speed clock divider, bus master clock select
circuit, subclock input circuit, and subclock waveform forming circuit. Figure 22.1 shows a block
diagram of the clock pulse generator.
EXTAL
XTAL
Oscillator
PFSEL
EXCL
Subclock
input circuit
PLL
multiplier
circuit
Subclock
waveform
forming
circuit
φ
φSUB
System clock
select circuit
φ
Medium-
speed clock
divider φ/2
to φ/32
Bus master
clock select
circuit
WDT_1
count clock
System clock
to φ pin
Internal clock
to peripheral
modules
Bus master clock
to CPU and DTC
Figure 22.1 Block Diagram of Clock Pulse Generator
The bus master clock is selected as either high-speed mode or medium-speed mode by software
according to the settings of the SCK2 to SCK0 bits in the standby control register. Use of the
medium-speed clock (φ/2 to φ/32) may be limited during CPU operation and when accessing the
internal memory of the CPU. The operation speed of the DTC and the external space access cycle
are thus stabilized regardless of the setting of medium-speed mode. For details on the standby
control register, see section 23.1.1, Standby Control Register (SBYCR).
The subclock input is controlled by software according to the EXCLE bit setting in the low power
control register. For details on the low power control register, see section 23.1.2, Low-Power
Control Register (LPWRCR).
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