HD64F2168 Datasheet, PDF (81/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Table 2.10 Block Data Transfer Instructions
Instruction Size
EEPMOV.B –
EEPMOV.W –
Function
if R4L ≠ 0 then
Repeat @ER5+ → @ER6+
R4L–1 → R4L
Until R4L = 0
else next:
if R4 ≠ 0 then
Repeat @ER5+ → @ER6+
R4–1 → R4
Until R4 = 0
else next:
Transfers a data block. Starting from the address set in ER5, transfers
data for the number of bytes set in R4L or R4 to the address location
set in ER6.
Execution of the next instruction begins as soon as the transfer is
completed.
2.6.2 Basic Instruction Formats
The H8S/2000 CPU instructions consist of 2-byte (1-word) units. An instruction consists of an
operation field (op), a register field (r), an effective address extension (EA), and a condition field
(cc).
Figure 2.11 shows examples of instruction formats.
• Operation field
Indicates the function of the instruction, the addressing mode, and the operation to be carried
out on the operand. The operation field always includes the first four bits of the instruction.
Some instructions have two operation fields.
• Register field
Specifies a general register. Address registers are specified by 3-bit, and data registers by 3-bit
or 4-bit. Some instructions have two register fields, and some have no register field.
• Effective address extension
8-, 16-, or 32-bit specifying immediate data, an absolute address, or a displacement.
• Condition field
Specifies the branching condition of Bcc instructions.
Rev. 3.00, 03/04, page 41 of 830