HD64F2168 Datasheet, PDF (334/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

CPU read cycle of ICRA or ICRC
T1
T2
φ
FTIA
Input capture
signal
Figure 11.10 Buffered Input Capture Timing (BUFEA = 1)
11.5.6 Timing of Input Capture Flag (ICF) Setting
The input capture flag, ICFA to ICFD, is set to 1 by the input capture signal. The FRC value is
simultaneously transferred to the corresponding input capture register (ICRA to ICRD). Figure
11.11 shows the timing of setting the ICFA to ICFD flag.
φ
Input capture
signal
ICFA to ICFD
FRC
N
ICRA to ICRD
N
Figure 11.11 Timing of Input Capture Flag (ICFA to ICFD) Setting
Rev. 3.00, 03/04, page 294 of 830