HD64F2168 Datasheet, PDF (154/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Table 6.3 Bit Settings and Bus Specifications of Basic Bus Interface
Areas
BRSTRM CS256E CPCSE
0
0
0
1
1
0
1
Basic Extended
Area
Basic extended
area
ABW, AST,
WMS1, WMS0,
WC1, WC0
256-kbyte
Extended Area
Used as basic
extended area
CP Extended Area (Basic
Mode)
Used as basic extended
area
ABWCP, ASTCP, WMS21,
WMS20, WC21, WC20
ABW256, AST256, Same as when CS256E = 0
WMS10, WC11,
WC10
1
0
0
Burst ROM
Used as burst
Used as burst ROM
interface*
ROM interface interface
1
ABW, AST,
WMS0, WC1,
WC0, BRSTS1,
BRSTS0
ABWCP, ASTCP, WMS21,
WMS20, WC21, WC20
1
0
1
ABW256, AST256, Same as when CS256E = 0
WMS10, WC11,
WC10
Note: * In the burst ROM interface, the bus width is specified by the ABW bit in WSCR, the
number of full access states (wait can be inserted) is specified by the AST bit in WSCR,
and the number of access cycles in burst access is specified regardless of the AST bit
setting.
Rev. 3.00, 03/04, page 114 of 830