HD64F2168 Datasheet, PDF (335/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

11.5.7 Timing of Output Compare Flag (OCF) setting
The output compare flag, OCFA or OCFB, is set to 1 by a compare-match signal generated when
the FRC value matches the OCRA or OCRB value. This compare-match signal is generated at the
last state in which the two values match, just before FRC increments to a new value. When the
FRC and OCRA or OCRB value match, the compare-match signal is not generated until the next
cycle of the clock source. Figure 11.12 shows the timing of setting the OCFA or OCFB flag.
φ
FRC
N
N+1
OCRA, OCRB
N
Compare-match
signal
OCFA, OCFB
Figure 11.12 Timing of Output Compare Flag (OCFA or OCFB) Setting
11.5.8 Timing of FRC Overflow Flag (OVF) Setting
The FRC overflow flag (OVF) is set to 1 when FRC overflows (changes from H'FFFF to H'0000).
Figure 11.13 shows the timing of setting the OVF flag.
φ
FRC
H'FFFF
H'0000
Overflow signal
OVF
Figure 11.13 Timing of Overflow Flag (OVF) Setting
Rev. 3.00, 03/04, page 295 of 830