HD64F2168 Datasheet, PDF (340/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

11.7.2 Conflict between FRC Write and Increment
If an FRC increment pulse is generated during the state after an FRC write cycle, the write takes
priority and FRC is not incremented. Figure 11.18 shows the timing for this type of conflict.
Write cycle of FRC
T1
T2
φ
Address
FRC address
Internal write
signal
FRC input
clock
FRC
N
M
Write data
Figure 11.18 Conflict between FRC Write and Increment
Rev. 3.00, 03/04, page 300 of 830