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| HD64F2168 Datasheet, PDF (175/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer | |||
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6.5.4 Basic Operation Timing in Address-Data Multiplex Extended Mode
(1) 8-Bit, 2-State Data Access Space: Figures 6.13 and 6.14 show the bus timing for an 8-bit, 2-
state access space. When an 8-bit access space is accessed, the upper half (AD15 to AD8) of the
data bus is used. Wait states cannot be inserted.
Ï
CPCS1
CS256
IOS
AH
RD
HWR
AD15 to AD8
Read Cycle
Address
T1
TAW
T2
Data
T3
T4
Write Cycle
Address
T1
TAW
T2
Data
T3
T4
Address
Data
Address
Data
Figure 6.13 Bus Timing for 8-Bit, 2-State Access Space
Ï
CPCS1
CS256
IOS
AH
RD
HWR
AD15 to AD8
Read Cycle
Address
T1
T2
Data
T3
T4
Write Cycle
Address
T1
T2
Data
T3
T4
Address
Data
Address
Data
Figure 6.14 Bus Timing for 8-Bit, 2-State Access Space
Rev. 3.00, 03/04, page 135 of 830
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