HD64F2168 Datasheet, PDF (28/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 12 8-Bit Timer (TMR)
Figure 12.1 Block Diagram of 8-Bit Timer (TMR_0 and TMR_1)............................................ 306
Figure 12.2 Block Diagram of 8-Bit Timer (TMR_Y and TMR_X).......................................... 307
Figure 12.3 Pulse Output Example ............................................................................................. 322
Figure 12.4 Count Timing for Internal Clock Input ................................................................... 323
Figure 12.5 Count Timing for External Clock Input .................................................................. 323
Figure 12.6 Timing of CMF Setting at Compare-Match ............................................................ 324
Figure 12.7 Timing of Toggled Timer Output by Compare-Match A Signal............................. 324
Figure 12.8 Timing of Counter Clear by Compare-Match ......................................................... 324
Figure 12.9 Timing of Counter Clear by External Reset Input................................................... 325
Figure 12.10 Timing of OVF Flag Setting ................................................................................. 325
Figure 12.11 Timing of Input Capture Operation....................................................................... 327
Figure 12.12 Timing of Input Capture Signal
(Input capture signal is input during TICRR and TICRF read) ............................. 328
Figure 12.13 Conflict between TCNT Write and Counter Clear ................................................ 330
Figure 12.14 Conflict between TCNT Write and Increment ...................................................... 331
Figure 12.15 Conflict between TCOR Write and Compare-Match ............................................ 332
Section 13 Watchdog Timer (WDT)
Figure 13.1 Block Diagram of WDT .......................................................................................... 338
Figure 13.2 Watchdog Timer Mode (RST/NMI = 1) Operation................................................. 344
Figure 13.3 Interval Timer Mode Operation............................................................................... 345
Figure 13.4 OVF Flag Set Timing .............................................................................................. 345
Figure 13.5 Output Timing of RESO signal ............................................................................... 346
Figure 13.6 Writing to TCNT and TCSR (WDT_0)................................................................... 348
Figure 13.7 Conflict between TCNT Write and Increment ........................................................ 349
Figure 13.8 Sample Circuit for Resetting the System by the RESO Signal................................ 350
Section 14 Serial Communication Interface (SCI, IrDA, and CRC)
Figure 14.1 Block Diagram of SCI_1......................................................................................... 353
Figure 14.2 Block Diagram of SCI_0 and SCI_2 ....................................................................... 354
Figure 14.3 Data Format in Asynchronous Communication
(Example with 8-Bit Data, Parity, Two Stop Bits)................................................... 380
Figure 14.4 Receive Data Sampling Timing in Asynchronous Mode ........................................ 382
Figure 14.5 Relation between Output Clock and Transmit Data Phase
(Asynchronous Mode).............................................................................................. 383
Figure 14.6 Basic Clock Examples When Average Transfer Rate is Selected (1) ..................... 384
Figure 14.7 Basic Clock Examples When Average Transfer Rate is Selected (2) ..................... 385
Figure 14.8 Sample SCI Initialization Flowchart ....................................................................... 386
Figure 14.9 Example of Operation in Transmission in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit)..................................................... 387
Figure 14.10 Sample Serial Transmission Flowchart ................................................................. 388
Rev. 3.00, 03/04, page xxviii of xl