SH7604 Datasheet, PDF (96/633 Pages) Hitachi Semiconductor – Hardware Manual

NMI
IR3–IR0
A3–A0
IVECF
D7–D0
Input/
output
control
UBC
DMAC
DIVU
FRT
SCI
WDT
REF
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
Priority
decision
logic
Com-
parator
Interrupt request
SR
I3 I2 I1 I0
CPU
IPR
ICR
IPRA, IPRB
Module bus
Bus
interface
VCRWDT
VCRWDT, VCRA–VCRD
Vector
number
INTC
Vector
number
DIV
DMAC
UBC: User break controller
ICR:
Interrupt control register
DMAC: Direct memory access controller IPRA/B: Interrupt priority level setting
DIVU: Division unit
registers A and B
FRT: Free-running timer
VCRWDT: Vector number setting register WDT
SCI: Serial communication interface
VCRA–D: Vector number setting registers A–D
WDT: Watchdog timer
SR:
Status register
REF: Refresh request within bus state controller
Figure 5.1 INTC Block Diagram
80