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| SH7604 Datasheet, PDF (468/633 Pages) Hitachi Semiconductor – Hardware Manual | |||
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Tp
CKIO
Upper
address
Lower
address
BS
Tr
Tc1
Tc2
Tc1
Tc2
tAD
tBSD
tBSD
CSn
RD/WR,
WE
RD
WEn,
CASxx,
DQMxx
D31âD0
DACKn
tCASD3
tCASD3
tASC
tWDD tWDS
tWDH1
tDACD3 tDACD1
WAIT
RAS,
CE
CAS,
OE
CKE
Note: The DACKn waveform shown is for the case where active-high has been specified.
Figure 15.50 DRAM Burst Write Cycle
(TRP = 1 Cycle, RCD = 1 Cycle, No Waits, PLL Off)
452
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