SH7604 Datasheet, PDF (140/633 Pages) Hitachi Semiconductor – Hardware Manual

C. Register settings: BARA = H'00027128, BAMRA = H'00000000, BBRA = H'005A
BARB = H'00031415, BAMRB = H'00000000, BBRB = H'0054
BDRB = H'00000000, BDMRB = H'00000000
BRCR = H'1000
Conditions set (channel A/channel B independent mode):
Channel A:
Address = H'00027128, address mask H'00000000
Bus cycle = CPU, instruction fetch (before execution), write , word
Channel B:
Address = H'00031415, address mask H'00000000
Data H'00000000, data mask H'00000000
Bus cycle = CPU, instruction fetch (before execution), read
(operand size not included in conditions)
A user break interrupt is not generated for channel A since the instruction fetch is not a write
cycle. A user break interrupt is not generated for channel B because the instruction fetch is for an
odd address.
D. Register settings: BARA = H'00037226, BAMRA = H'00000000, BBRA = H'005A
BARB = H'0003722E, BAMRB = H'00000000, BBRB = H'0056
BDRB = H'00000000, BDMRB = H'00000000
BRCR = H'1010
Conditions set (channel A → channel B sequential mode):
Channel A:
Address = H'00037226, address mask H'00000000
Bus cycle = CPU, instruction fetch (before execution), write, word
Channel B:
Address = H'0003722E, address mask H'00000000
Data H'00000000
Data mask H'00000000
Bus cycle = CPU, instruction fetch (before execution), read, word
The break for channel A is a write cycle, so conditions are not satisfied; since the sequence
conditions are not met, no user break interrupt occurs.
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