SH7604 Datasheet, PDF (253/633 Pages) Hitachi Semiconductor – Hardware Manual

9.2.4 DMA Channel Control Registers 0 and 1 (CHCR0 and CHCR1)
Bit: 31
30
29
…
19
18
17
16
Bit name: —
—
—
…
—
—
—
—
Initial value: 0
0
0
…
0
0
0
0
R/W: R
R
R
…
R
R
R
R
Bit: 15
14
13
12
11
10
9
8
Bit name: DM1 DM0 SM1 SM0
TS1
TS0
AR
AM
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
Bit name: AL
DS
DL
TB
TA
IE
TE
DE
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/(W)* R/W
Note: Only 0 can be written, to clear the flag.
DMA channel control registers 0 and 1 (CHCR0 and CHCR1) are 32-bit read/write registers that
control the DMA transfer mode. They also indicate the DMA transfer status. Only the lower 16 of
the 32 bits are valid. They are written as 32-bit values, including the upper 16 bits. Write the initial
values to the upper 16 bits. These bits always read 0. The registers are initialized to H'00000000
by a reset and in standby mode. Values are retained during a module standby.
• Bits 15 and 14—Destination Address Mode Bits 1, 0 (DM1, DM0): Select whether the DMA
destination address is incremented, decremented or left fixed (in single address mode, DM1
and DM0 are ignored when transfers are made from a memory-mapped external device, on-
chip peripheral module, or external memory to an external device with DACK). DM1 and
DM0 are initialized to 00 by a reset and in standby mode. Values are retained during a module
standby.
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