SH7604 Datasheet, PDF (376/633 Pages) Hitachi Semiconductor – Hardware Manual

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Serial
data
Start
bit
0 D₀
Parity Stop Start
Data bit bit bit
D₁
D₇ 0/1 1 0 D₀
Parity Stop
Data _bit bit
D₁
D₇ 0/1 1
1
Idle
(mark)
state
TDRE
TEND
TXI interrupt
request
generated
TXI interrupt
handler writes
data to TDR
and clears
TDRE bit to 0
TXI interrupt
request
generated
1 frame
TEI interrupt
request
generated
Example: 8-bit data with parity and one stop bit
Figure 13.6 Example of SCI Transmit Operation in Asynchronous Mode
(8-Bit Data with Parity and One Stop Bit)
Receiving Serial Data (Asynchronous Mode): Figure 13.7 shows a sample flowchart for
receiving serial data. The procedure for receiving serial data is as follows:
1. Receive error handling: if a receive error occurs, read the ORER, PER and FER bits of the SSR
to identify the error. After executing the necessary error handling, clear ORER, PER and FER
all to 0. Receiving cannot resume if ORER, PER or FER remain set to 1.
2. SCI status check and receive-data read: read the serial status register (SSR), check that RDRF
is set to 1, then read receive data from the receive data register (RDR) and clear RDRF to 0.
The RXI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1.
3. To continue receiving serial data: read the RDRF and RDR bits and clear RDRF to 0 before the
stop bit of the current frame is received. If the DMAC is started by a receive-data-full interrupt
(RXI) to read RDR, the RDRF bit is cleared automatically so this step is unnecessary.
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