SH7604 Datasheet, PDF (208/633 Pages) Hitachi Semiconductor – Hardware Manual

7.7.2 Basic Timing
Figure 7.38 shows the basic pseudo-SRAM access timing. Tp is the precharge cycle, Tr is the CE
assert cycle, Tc1 is the write data output and BS assert cycle, and Tc2 is the read data fetch cycle.
When accesses are consecutive, precharge cycle Tp overlaps the Tc2 cycle of the previous access,
so reads or writes can be performed in a minimum of 3 cycles each.
Tp
CKIO
Tr
Tc1
Tc2
A26–A1
CS3
BS
CE
OE
Read
RD
WEn
D31–D0
OE
Write
RD
WEn
D31–D0
Figure 7.38 Basic Access Timing
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