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| SH7604 Datasheet, PDF (451/633 Pages) Hitachi Semiconductor – Hardware Manual | |||
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CKIO
Upper
address
Lower
address
BS
CSn
RD/WR,
WE
RD
WEn,
CASxx,
DQMxx
D31âD0
Tp
tAD
Tmw
tAD
tAD
tBSD
tCSD1
tRWD
tBSD
tCSD1
tCSD1
tRWD
tDQMD
DACKn
WAIT
RAS,
CE
CAS,
OE
tRASD1
tRASD1
tRASD1
tCSD1
tCSD1
CKE
Figure 15.33 Synchronous DRAM Mode Register Write Cycle (TRP = 1 Cycle)
435
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