SH7604 Datasheet, PDF (298/633 Pages) Hitachi Semiconductor – Hardware Manual

Transfer width: Byte, word, longword
Transfer bus mode: Burst mode
Transfer address mode: Dual mode
DREQ detection method: Level detection
DACK output timing: DMAC write
Bus cycle: Basic bus cycle
Clock
DREQ
DACK
*
1st
acceptance
*
2nd
acceptance
*
3rd
acceptance
Bus
cycle
CPU
DMAC read
DMAC
invalid write
DMAC write
Note: Request detection (The points when the 1st and 2nd acceptances occur vary with the
type of wait.)
Figure 9.51 Timing of DREQ Pin Input Detection in Burst Mode with Level Detection (6)
Acknowledge signals for request signals are output 6 cycles later, at the soonest. Even when
the request signal is dropped within 0.5 cycle of the output of the acknowledge signal, the 2nd
request in figure 9.51 is accepted. This means that two DMA transfers are executed even when
the request for the 1st acknowledge signal drops out.
Examples of Handling of Request Signal Acceptance: When DREQ level acceptance is used in
the cycle-steal mode, the following methods can be used when the request signal is received:
1. Control the number of transfers by TCR
2. Use edge for request acceptance
3. Perform acknowledge signal output at the DMAC write timing
Additional Cautions when Emulators Are Used: When DREQ level acceptance is by an
emulator in cycle-steal mode, the timing of request signal acceptance is 2 cycles after the output of
the acknowledge signal, so it differs from ordinary specifications. This means that when DMAC
operation is emulated, the timing is somewhat different, which may have other ramifications.
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