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| SH7604 Datasheet, PDF (558/633 Pages) Hitachi Semiconductor – Hardware Manual | |||
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CKIO
Upper
address
Lower
address
BS
Tp
Tr
Tc1
Tc2
Tc1
Tc2
tAD
tBSD
tBSD
CSn
RD/WR,
WE
RD
WEn,
CASxx,
DQMxx
D31âD0
DACKn
tRSD1
tRSD1
tRDH6
tRDS1
tRDH6
tRDS1
tDACD2 tDACD1
WAIT
RAS,
CE
CAS,
OE
tOED1
tOED1
CKE
Note: The DACKn waveform shown is for the case where active-high has been specified.
Figure 16.56 Pseudo-SRAM Read Cycle
(Static Column Mode, PLL On, TRP = 1 Cycle, RCD = 1 Cycle, No Waits)
542
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