SH7604 Datasheet, PDF (353/633 Pages) Hitachi Semiconductor – Hardware Manual

Bit: 7
Bit name: C/A
Initial value: 0
R/W: R/W
6
5
CHR
PE
0
0
R/W R/W
4
3
2
1
0
O/E STOP MP CKS1 CKS0
0
0
0
0
0
R/W R/W R/W R/W R/W
• Bit 7—Communication Mode (C/A): Selects whether the SCI operates in asynchronous or
clocked synchronous mode.
Bit 7: C/A
0
1
Description
Asynchronous mode
Clocked synchronous mode
(Initial value)
• Bit 6—Character Length (CHR): Selects 7-bit or 8-bit data in asynchronous mode. In clocked
synchronous mode, the data length is always eight bits, regardless of the CHR setting.
Bit 6: CHR
0
1
Description
8-bit data
(Initial value)
7-bit data. (When 7-bit data is selected, the MSB (bit 7) of the transmit
data register is not transmitted.)
• Bit 5—Parity Enable (PE): Selects whether to add a parity bit to transmit data and to check the
parity of receive data, in asynchronous mode. In clocked synchronous mode, a parity bit is
neither added nor checked, regardless of the PE setting.
Bit 5: PE
0
1
Description
Parity bit not added or checked
(Initial value)
Parity bit added and checked. When PE is set to 1, an even or odd
parity bit is added to transmit data, depending on the parity mode (O/E)
setting. Receive data parity is checked according to the even/odd (O/E)
mode setting.
• Bit 4—Parity Mode (O/E): Selects even or odd parity when parity bits are added and checked.
The O/E setting is used only in asynchronous mode and only when the parity enable bit (PE) is
set to 1 to enable parity addition and checking. The O/E setting is ignored in clocked
synchronous mode, and in asynchronous mode when parity addition and checking is disabled.
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