SH7604 Datasheet, PDF (490/633 Pages) Hitachi Semiconductor – Hardware Manual

15.3.4 DMAC Timing
Table 15.10 DMAC Timing (Conditions: V_CC = 5.0 V ±10%, Ta = –20 to +75°C)
Item
Symbol Min
Max Unit Figure
DREQ0, DREQ1 setup time (PLL Off, On)
t_DRQS
DREQ0, DREQ1 setup time (PLL On, 1/4 cycle delay) t_DRQS
DREQ0, DREQ1 hold time (PLL Off, On)
t_DRQH
DREQ0, DREQ1 hold time (PLL On, 1/4 cycle delay) t_DRQH
DREQ0, DREQ1 low level width
t_DRQW
30
—
30 – 1/4 tcyc —
15
—
1/4 tcyc + 15 —
1.5
—
ns 15.72
ns
ns
ns
t_cyc
CKIO
DREQ0, DREQ1
level
DREQ0, DREQ1
edge
DREQ0, DREQ1
level cancellation
t_DRQS
t_DRQS
t_DRQH
t_DRQS
Figure 15.72 DREQ0, DREQ1 Input Timing
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