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SH7604 Datasheet, PDF (574/633 Pages) Hitachi Semiconductor – Hardware Manual | |||
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16.3.4 DMAC Timing
Table 16.10 DMAC Timing (Conditions: VCC = 3.0 to 5.5 V, Ta = â20 to +75°C)
Item
Symbol Min
Max Unit Figure
DREQ0, DREQ1 setup time (PLL Off, On)
tDRQS
DREQ0, DREQ1 setup time (PLL On, 1/4 cycle delay) tDRQS
DREQ0, DREQ1 hold time (PLL Off, On)
tDRQH
DREQ0, DREQ1 hold time (PLL On, 1/4 cycle delay) tDRQH
DREQ0, DREQ1 low level width
tDRQW
50
â
50 â 1/4 tcyc â
50
â
1/4 tcyc + 50 â
1.5
â
ns 16.72
ns
ns
ns
tcyc
CKIO
DREQ0, DREQ1
level
DREQ0, DREQ1
edge
DREQ0, DREQ1
level cancellation
tDRQS
tDRQS
tDRQH
tDRQS
Figure 16.72 DREQ0, DREQ1 Input Timing
558
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