SH7604 Datasheet, PDF (136/633 Pages) Hitachi Semiconductor – Hardware Manual

6.3 Operation
6.3.1 Flow of the User Break Operation
The flow from setting of break conditions to user break interrupt exception handling is described
below:
1. The break addresses are set in the break address registers (BARA, BARB), the masked
addresses are set in the break address mask registers (BAMRA, BAMRB), the break data is set
in the break data register (BDRB), and the masked data is set in the break data mask register
(BDMRB). The breaking bus conditions are set in the break bus cycle registers (BBRA,
BBRB). The three groups of the BBRA and BBRB registers—CPU cycle/peripheral cycle
select, instruction fetch/data access select, and read/write select— are each set. No user break
interrupt will be generated if even one of these groups is set with 00. The conditions are set in
the respective bits of the BRCR register.
2. When the set conditions are satisfied, the UBC sends a user break interrupt request to the
interrupt controller. When conditions match, the CPU condition match flags (CMFCA,
CMFCB) and peripheral condition match flags (CMFPA, CMFPB) for the respective channels
are set.
3. The interrupt controller checks the user break interrupt’s priority level. The user break
interrupt has priority level 15, so it is accepted only if the interrupt mask level in bits I3–I0 in
the status register (SR) is 14 or lower. When the I3–I0 bit level is 15, the user break interrupt
cannot be accepted but it is held pending until user break interrupt exception handling can be
carried out. Section 5, Interrupt Controller, describes the handling of priority levels in greater
detail.
4. When the priority is found to permit acceptance of the user break interrupt, the CPU starts user
break interrupt exception handling.
5. The appropriate condition match flag (CMFCA, CMFPA, CMFCB, CMFPB) can be used to
check if the set conditions match or not. The flags are set by the matching of the conditions,
but they are not reset. 0 must first be written to them before they can be used again.
6.3.2 Break on Instruction Fetch Cycle
1. When CPU/instruction fetch/read/word is set in the break bus cycle registers (BBRA/BBRB),
the break condition becomes the CPU’s instruction fetch cycle. Whether it breaks before or
after the execution of the instruction can then be selected for the appropriate channel with the
PCBA/PCBB bit in the break control register (BRCR).
2. The instruction fetch cycle always fetches 32 bits (two instructions). Only one bus cycle
occurs, but breaks can be placed on each instruction individually by setting the respective
addresses in the break address registers (BARA, BARB).
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