 English |
|
|
|
|
|
|
|
| SH7604 Datasheet, PDF (439/633 Pages) Hitachi Semiconductor – Hardware Manual | |||
| |||
| ◁ |
Tr
Tc
Td1
Td2
Td3
Td4
CKIO
tAD
tAD
Upper
address
tAD
Lower
address
tBSD
tBSD
tBSD
tBSD
BS
tCSD1
tCSD1
CSn
RD/WR,
WE
tRWD
tRWD
tRSD1
RD
WEn,
CASxx,
DQMxx
tDQMD
tRDS3 tRDH4
tDQMD
D31âD0
WAIT
RAS,
CE
CAS,
OE
tRASD1 tRASD1
tCASD1 tCASD1
tRASD1
tCASD1 tCASD1
CKE
Note: The dotted line shows the waveform when synchronous DRAM in another CS space is
accessed.
Figure 15.21 Synchronous DRAM Single Read Bus Cycle
(RCD = 1 Cycle, CAS Latency = 1 Cycle, Bursts = 4, PLL On)
423
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese