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| SH7604 Datasheet, PDF (435/633 Pages) Hitachi Semiconductor – Hardware Manual | |||
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CKIO
A26âA0
BS
CSn
RD/WR,
WE
RD
WEn,
CASxx,
DQMxx
D31âD0
DACKn
T1
tAD tAS1
T2
tAD
tBSD
tBSD
tAH2
tCSD1
tRWD
tCSD3
tRWD
tRSD2
tWED2
tWDD
tDON
tDACD1
tRSD2
tWED2
tWDH2
tWDH1
tDOF
tDACD3
WAIT
RAS,
CE
CAS,
OE
Notes: 1.
2.
CKE
The dotted line shows the waveform when synchronous DRAM is connected.
The DACKn waveform shown is for the case where active-high has been specified.
Figure 15.17 Basic Write Cycle (No Waits, PLL Off)
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