 English |
|
|
|
|
|
|
|
| SH7604 Datasheet, PDF (562/633 Pages) Hitachi Semiconductor – Hardware Manual | |||
| |||
| ◁ |
CKIO
Address
BS
CSn
RD/WR,
WE
RD
WEn,
CASxx,
DQMxx
D31âD0
DACKn
Tp
Tr
tAD
Tc1
Tc2
tAD
tCSD1
tBSD
tBSD
tCSD1
tRWD
tRSD2
tWED2
tRWD
tRSD2
tRSD2
tRDS2
tRDH6
tDACD1
tDACD3
WAIT
RAS,
CE
CAS,
OE
tCED2
tCED2
tAS2
tCED2
tOED2
tOED2
tOED2
CKE
Note: The DACKn waveform shown is for the case where active-high has been specified.
Figure 16.60 Pseudo-SRAM Read Cycle
(PLL Off, TRP = 1 Cycle, RCD = 1 Cycle, No Waits)
546
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese