SH7604 Datasheet, PDF (156/633 Pages) Hitachi Semiconductor – Hardware Manual

7.2.3 Wait Control Register (WCR)
Bit:
Bit name:
Initial value:
R/W:
15
IW31
1
R/W
14
IW30
0
R/W
13
IW21
1
R/W
12
IW20
0
R/W
11
IW11
1
R/W
10
IW10
0
R/W
9
IW01
1
R/W
8
IW00
0
R/W
Bit:
Bit name:
Initial value:
R/W:
7
W31
1
R/W
6
W30
1
R/W
5
W21
1
R/W
4
W20
1
R/W
3
W11
1
R/W
2
W10
1
R/W
1
W01
1
R/W
0
W00
1
R/W
Do not access a space other than CS0 until the settings for register initialization are completed.
• Bits 15 to 8—Idles between Cycles for Areas 3 to 0 (IW31–IW00): These bits specify idle
cycles inserted between consecutive accesses to different areas. Idles are used to prevent data
conflict between ROM or the like, which is slow to turn the read buffer off, and fast memories
and I/O interfaces. Even when access is to the same area, idle cycles must be inserted when a
read access is followed immediately by a write access. The idle cycles to be inserted comply
with the specification for the previously accessed area.
IW31, IW21, IW11, IW01
0
1
IW30, IW20, IW10, IW00
0
1
0
1
Description
No idle cycle
One idle cycle inserted
Two idle cycles inserted
Reserved (do not set)
(Initial value)
• Bits 7 to 0—Wait Control for Areas 3 to 0 (W31–W00)
During the basic cycle:
W31, W21, W11, W01
0
0
1
1
W30, W20, W10, W00
0
1
0
1
Description
External wait input disabled without wait
External wait input enabled with one wait
External wait input enabled with two waits
Complies with the long wait specification of
bus control register 1 (BCR1). External wait
input is enabled
(Initial value)
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