SH7604 Datasheet, PDF (19/633 Pages) Hitachi Semiconductor – Hardware Manual

Clock Pulse Generator (CPG)/Phase Locked Loop (PLL):
• On-chip clock pulse generator
• Crystal clock source or external clock source can be selected
• Clock multiplication (×1, ×2, ×4), PLL synchronization, or 90° phase shift can be selected
• Supports clock pause function for frequency change of external clock
Bus State Controller (BSC):
• Supports external memory access
 32-bit external data bus
• Memory address space divided into four areas. It is possible to set the following characteristics
for each area (32 Mbyte linear):
 Bus size (8, 16, or 32 bits)
 Number of wait cycles settable or not settable
 Setting the memory space type simplifies connection to DRAM, synchronous DRAM,
pseudo-SRAM, and burst ROM
 Outputs signals RAS, CAS, CE, and OE corresponding to DRAM, synchronous DRAM,
and pseudo-SRAM areas
 Tp cycles can be generated to assure RAS precharge time
 Address multiplexing is supported internally, so DRAM and synchronous DRAM can be
connected directly
 Outputs chip select signals (CS0 to CS3) for each area
• DRAM/synchronous DRAM/pseudo-SRAM refresh functions
 Programmable refresh interval
 Supports CAS-before-RAS refresh and self-refresh modes
• DRAM/synchronous DRAM/pseudo-SRAM burst access function
 Supports high-speed access modes for DRAM/synchronous DRAM/pseudo-SRAM
• Wait cycles can be inserted by an external WAIT signal
Cache Memory:
• 4 kbytes
• 64 entries, 4-way set associative, 16-byte line length
• Write-through data writing method
• LRU replacement algorithm
• 2 kbytes of the cache can be used as 2-kbyte internal RAM
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