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SH7604 Datasheet, PDF (429/633 Pages) Hitachi Semiconductor – Hardware Manual | |||
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Table 15.8 Bus Timing With PLL Off (CKIO Input) [Mode 6] (cont)
(Conditions: VCC = 5.0 V ±10%, Ta = â20 to +75°C)
Item
Symbol Min
Max
Unit Figures
WAIT setup time
tWTS
20
â
ns 15.19, 15.43, 15.55,
15.67, 15.70
WAIT hold time
tWTH
15
â
ns 15.19, 15.43, 15.55,
15.67, 15.70
RAS delay time 1 (SDRAM) tRASD1
â
25
ns 15.38
RAS delay time 3 (DRAM) tRASD3
10
25
ns 15.47
CAS delay time 1 (SDRAM) tCASD1
â
25
ns 15.38
CAS delay time 3 (DRAM) tCASD3
10
25
ns 15.47
DQM delay time
tDQMD
â
25
ns 15.38
CKE delay time
tCKED
â
25
ns 15.37
CE delay time 2
tCED2
10
25
ns 15.60
OE delay time 2
tOED2
â
25
ns 15.60
IVECF delay time
tIVD
â
25
ns 15.69
WE setup time
tWES1
0
â
ns 15.16
Address setup time 1
tAS1
0
â
ns 15.17
Address setup time 2
tAS2
3
â
ns 15.60
Address hold time 2
tAH2
0
â
ns 15.17
Row address setup time tASR
3
â
ns 15.47
Column address setup time tASC
3
â
ns 15.47
Write command setup time tWCS
3
â
ns 15.48
Write data setup time
tWDS
3
â
ns 15.48
Address input setup time* tASIN
15
â
ns 15.71
Address input hold time* tAHIN
10
â
ns 15.71
BS input setup time*
tBSS
15
â
ns 15.71
BS input hold time*
tBSH
10
â
ns 15.71
Read/write input setup time* tRWS
15
â
ns 15.71
Read/write input hold time* tRWH
10
â
ns 15.71
Data buffer on time
tDON
â
25
ns 15.17, 15.39, 15.48,
15.61
Data buffer off time
tDOF
â
25
ns 15.17, 15.39, 15.48,
15.61
Note: When the external addresses monitor function is used, the PLL must be on.
413
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