SH7604 Datasheet, PDF (230/633 Pages) Hitachi Semiconductor – Hardware Manual

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28
Address
3
Access space
specification address
9
3
0
19
Tag address
Figure 8.2 Address
6
4
Entry address
Byte address
in line
8.2 Cache Control Register (CCR)
Table 8.1 Cache Control Register
Name
Cache control register
Abbrev.
CCR
R/W Initial Value
R/W H'00
Address
H'FFFFFE92
The cache control register (CCR) is used for cache control. CCR must be set and the cache must
be initialized before use.
Bit: 7
6
5
Bit name: W1
W0
—
Initial value: 0
0
0
R/W: R/W R/W
R
4
3
2
1
0
CP
TW
OD
ID
CE
0
0
0
0
0
R/W R/W R/W R/W R/W
• Bits 7 and 6—Way Specification (W1 to W0): W1 and W0 specify the way when an address
array is directly accessed by address specification.
Bit 7: W1
0
1
Bit 6: W0
0
1
0
1
Description
Way 0
Way 1
Way 2
Way 3
(Initial value)
• Bit 5—Reserved: This bit always reads 0. The write value should always be 0.
• Bit 4—Cache Purge (CP): CP is a cache purge bit. When 1 is written to CP, all cache entries
and all valid bits and LRU bits of the way are initialized to 0. After initialization is complete,
the CP bit reverts to 0. The CP bit always reads 0.
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