SH7604 Datasheet, PDF (86/633 Pages) Hitachi Semiconductor – Hardware Manual

4.2.2 Power-On Reset
When the NMI pin is high and the RES pin is driven low, the device performs a power-on reset.
For a reliable reset, the RES pin should be kept low for at least the duration of the oscillation
settling time (when the PLL circuit is halted) or for 20 clock cycles (when the PLL circuit is
running). During a power-on reset, the CPU’s internal state and all on-chip peripheral module
registers are initialized. See appendix A, Pin States, for the state of individual pins in the power-on
reset state.
In a power-on reset, power-on reset exception handling starts when the NMI pin is kept high and
the RES pin is first driven low for a set period of time and then returned to high. The CPU will
then operate as follows:
1. The initial value (execution start address) of the program counter (PC) is fetched from the
exception vector table.
2. The initial value of the stack pointer (SP) is fetched from the exception vector table.
3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3–I0) of
the status register (SR) are set to H'F (1111).
4. The values fetched from the exception vector table are set in the PC and SP, and the program
begins executing.
4.2.3 Manual Reset
When the NMI pin is low and the RES pin is driven low, the device executes a manual reset. For a
reliable reset, the RES pin should be kept low for at least 20 clock cycles. During a manual reset,
the CPU’s internal state is initialized. Registers of all on-chip peripheral modules except the bus
state controller (BSC), user break controller (UBC) and the frequency modification register are
initialized. Since the BSC is not affected, the DRAM and synchronous DRAM refresh control
functions remain operational even if the manual reset state continues for a long period of time.
When the chip enters the manual reset state in the middle of a bus cycle, manual reset exception
handling does not start until the bus cycle has ended. Thus, manual resets do not abort bus cycles.
See appendix A, Pin States, for the state of individual pins in the manual reset state.
In a manual reset, manual reset exception handling starts when the NMI pin is kept low and the
RES pin is first kept low for a set period of time and then returned to high. The CPU will then
operate in the same way as for a power-on reset.
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