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| SH7604 Datasheet, PDF (569/633 Pages) Hitachi Semiconductor – Hardware Manual | |||
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CKIO
A26âA0
BS
CSn
RD/WR,
WE
RD
WEn,
CASxx,
DQMxx
D31âD0
DACKn
WAIT
T1
TW
T2
TW
T2
tAD
tAD
tAD
tBSD
tBSD
tCSD1
tRWD
tRSD2
tBSD
tBSD
tCSD3
tRWD
tRSD2
tRSD2
tRSD2
tWED2
tDACD1
tRDS2
tRDH2
tRDS2
tRDH2
tDACD3 tDACD1
tDACD3
tWTS tWTH
tWTS tWTH
RAS,
CE
CAS,
OE
CKE
Note: The DACKn waveform shown is for the case where active-high has been specified.
Figure 16.67 Burst ROM Read Cycle (PLL Off, 1 Wait)
553
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