SH7604 Datasheet, PDF (129/633 Pages) Hitachi Semiconductor – Hardware Manual

Bit 7: CPA1
0
1
Bit 6: CPA0
0
1
0
1
Description
No channel A user break interrupt occurs
Break only on CPU cycles
Break only on peripheral cycles
Break on both CPU and peripheral cycles
(Initial value)
• Bits 5 and 4—Instruction Fetch/Data Access Select A (IDA1, IDA0): These bits select whether
to break channel A on instruction fetch and/or data access cycles.
Bit 5: IDA1
0
1
Bit 4: IDA0
0
1
0
1
Description
No channel A user break interrupt occurs
(Initial value)
Break only on instruction fetch cycles
Break only on data access cycles
Break on both instruction fetch and data access cycles
• Bits 3 and 2—Read/Write Select A (RWA1, RWA0): These bits select whether to break
channel A on read and/or write cycles.
Bit 3: RWA1
0
1
Bit 2: RWA0
0
1
0
1
Description
No channel A user break interrupt occurs
Break only on read cycles
Break only on write cycles
Break on both read and write cycles
(Initial value)
• Bits 1 and 0—Operand Size Select A (SZA1, SZA0): These bits select bus cycle operand size
as a channel A break condition.
Bit 1: SZA1
Bit 0: SZA0 Description
0
0
Operand size is not a break condition
(Initial value)
1
Break on byte access
1
0
Break on word access
1
Break on longword access
Note:
When breaking on an instruction fetch, set the SZA0 bit to 0. All instructions are considered
to be word-size accesses (instruction fetches are always longword). Operand size is word
for instructions or determined by the operand size specified for the CPU/DMAC data
access. It is not determined by the bus width of the space being accessed.
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