SH7604 Datasheet, PDF (345/633 Pages) Hitachi Semiconductor – Hardware Manual

12.3.4 Timing of Overflow Flag (OVF) Setting
In interval timer mode, when WTCNT overflows, the OVF flag in WTCSR is set to 1 and an
interval timer interrupt (ITI) is requested (figure 12.6).
φ
WTCNT
Overflow signal
(internal signal)
H'FF H'00
OVF
Figure 12.6 Timing of OVF Setting
12.3.5 Timing of Watchdog Timer Overflow Flag (WOVF) Setting
When WTCNT overflows the WOVF flag in RSTCSR is set to 1 and a WDTOVF signal is output.
When the RSTE bit is set to 1, WTCNT overflow enables an internal reset signal to be generated
for the entire chip (figure 12.7).
φ
WTCNT
Overflow signal
(internal signal)
WOVF
H'FF H'00
Figure 12.7 Timing of WOVF Setting
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