SH7604 Datasheet, PDF (168/633 Pages) Hitachi Semiconductor – Hardware Manual

chip stays in read status, so there is a danger of conflicts occurring with output when this is used to
control the external data buffer.
T1
T2
CKIO
A26–A0
CSn
RD/WR
Read
RD
D31–D0
Write
WEn
D31–D0
BS
Figure 7.7 Basic Timing of Ordinary Space Access
Figure 7.8 shows an example of a 32-bit data width SRAM connection, figure 7.9 a 16-bit data
width SRAM connection, and figure 7.10 an 8-bit data width SRAM connection.
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