SH7604 Datasheet, PDF (142/633 Pages) Hitachi Semiconductor – Hardware Manual

6.3.7 Usage Notes
1. UBC registers can only be read or written to by the CPU.
2. When set for a sequential break, conditions match when a match of channel B conditions
occurs some time after the bus cycle in which a channel A match occurs. This means that the
conditions will not be satisfied when set for a bus cycle in which channel A and channel B
occur simultaneously. Since the CPU uses a pipeline structure, the order of the instruction
fetch cycle and memory cycle is fixed, so sequential conditions will be satisfied when the
respective channel conditions are met in the order the bus cycles occur.
3. When set for sequential conditions (the SEQ bit in BRCR is 1) and the instruction fetch cycle
of the channel A CPU is set as a condition, set channel A for before instruction execution
(PCBA bit in BRCR is 0).
4. When register settings are changed, the write values usually become valid after three cycles.
For on-chip memory, instruction fetches get two instructions simultaneously. If a break
condition is set on the fetch of the second of these two instructions but the contents of the UBC
registers are changed so as to alter the break condition immediately after the first of the two
instructions is fetched, a user break interrupt will still occur before the second instruction. To
ensure the timing of the change in the setting, read the register written last as a dummy. The
changed settings will be valid thereafter.
5. When a user break interrupt is generated upon a match of the instruction fetch condition and
the conditions match again in the UBC while the exception handling service routine is
executing, the break will cause exception handling when the I3–I0 bits in SR are set to 14 or
lower. When masking addresses, when setting instruction fetch and after-execution as break
conditions, and when executing in steps, the UBC’s exception service routine should not cause
a match of addresses with the UBC.
6. When the emulator is used, the UBC is used on the emulator system side to implement the
emulator's break function. This means none of the UBC functions can be used when the
emulator is being used.
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