SH7604 Datasheet, PDF (603/633 Pages) Hitachi Semiconductor – Hardware Manual

INTC
Vector number setting registers
DMA0 and DMA1 (VCRDMA0,
VCRDMA1)
H'FFFFFFA0 (channel 0)
H'FFFFFFA8 (channel 1)
32
Bit
Item
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Bit Name — — — — — — — — — — — — — — — —
Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W
RRRR RRRR RRRR RRRR
Item
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit Name — — — — — — — — VC7 VC6 VC5 VC4 VC3 VC2 VC1 VC0
Initial Value 0 0 0 0 0 0 0 0 — — — — — — — —
R/W
R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
7 to 0 Vector number bits (VC7–VC0)
Description
These bits set the vector number at the end of DMA
transfer
Interrupt control register (ICR) H'FFFFFEE0
8/16
Bit
Item
15 14 13 12 11 10 9 8
7654 3210
Bit Name
VEC
NMIL — — — — — — NMIE — — — — — — — MD
Initial Value 0/1* 0 0 0 0 0 0 0 — — — — — — — —
R/W
R R R R R R R R/W R R R R R R R R/W
Note: When NMI input is high: 1; when NMI input is low: 0
Bit
Bit Name
Value
Description
15 NMI input level (NMIL) 0 NMI input level is low
1 NMI input level is high
8 NMI edge select (NMIE) 0 Interrupt request is detected on falling edge of NMI input
(Initial value)
1 Interrupt request is detected on rising edge of NMI input
1 RL interrupt vector
0 Auto-vector mode, automatically set internall
(Initial value)
mode select (VECMD) 1 External vector mode, external input
587