SH7604 Datasheet, PDF (296/633 Pages) Hitachi Semiconductor – Hardware Manual

Transfer width: Byte, word, longword
Transfer bus mode: Burst mode
Transfer address mode: Single mode
DREQ detection method: Level detection
DACK output timing: DMAC cycle
Bus cycle: Basic bus cycle
Clock
DREQ
*
1st
accept-
ance
Bus
cycle
DACK
**
*
2nd
3rd
accept- accept-
ance ance
4th
accept-
ance
*
5th
accept-
ance
*
6th
accept-
ance
DMAC read 1 DMAC read 2 DMAC read 3 DMAC read 4 DMAC read 5 DMAC read 6
Note: Request detection (The points when the acceptances occur vary with the type of wait.)
Figure 9.48 Timing of DREQ Pin Input Detection in Burst Mode with Level Detection (3)
(Data Transfer from Normal Space to Device, Using Evaluation Chip)
Transfer width: Byte, word, longword
Transfer bus mode: Burst mode
Transfer address mode: Single mode
DREQ detection method: Level detection
DACK output timing: DMAC cycle
Bus cycle: Basic bus cycle
Clock
DREQ
Bus
cycle
DACK
*
**
*
*
*
1st
2nd 3rd
accept- accept- accept-
ance ance ance
4th
accept-
ance
5th
accept-
ance
6th
accept-
ance
Invalid DMAC Invalid DMAC Invalid
write write 1 write write 2 write
DMAC Invalid DMAC Invalid
write 3 write write 4 write
DMAC
write 5
Note: Request detection (The points when the acceptances occur vary with the type of wait.)
Figure 9.49 Timing of DREQ Pin Input Detection in Burst Mode with Level Detection (4)
(Data Transfer from Device to Normal Memory, Using Evaluation Chip)
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