SH7604 Datasheet, PDF (200/633 Pages) Hitachi Semiconductor – Hardware Manual

7.6.3 Basic Timing
The basic timing of a DRAM access is 3 cycles. Figure 7.31 shows the basic DRAM access
timing. Tp is the precharge cycle, Tr is the RAS assert cycle, Tc1 is the CAS assert cycle, and Tc2
is the read data fetch cycle. When accesses are consecutive, the Tp cycle of the next access
overlaps the Tc2 cycle of the previous access, so accesses can be performed in a minimum of 3
cycles each.
Tp
Tr
Tc1
Tc2
CKIO
A26–A14
A13–A1
RAS
CASn
RD/WR
Read
RD
D31–D0
RD/WR
Write
RD
D31–D0
CS3
BS
Figure 7.31 Basic Access Timing
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