SH7604 Datasheet, PDF (110/633 Pages) Hitachi Semiconductor – Hardware Manual

5.3.7 Vector Number Setting Register D (VCRD)
Vector number setting register D (VCRD) is a 16-bit read/write register that sets the FRT overflow
interrupt vector number (0–127). VCRD is initialized to H'0000 by a reset. It is not initialized in
standby mode.
Bit: 15
14
13
12
11
10
9
8
Bit name: — FOVV6 FOVV5 FOVV4 FOVV3 FOVV2 FOVV1 FOVV0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
Bit name: —
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
• Bits 15, 7–0—Reserved: These bits always read 0. The write value should always be 0.
• Bits 14 to 8—Free-Running Timer (FRT) Overflow Interrupt Vector Number (FOVV6–
FOVV0): These bits set the vector number for the free-running timer (FRT) overflow interrupt
(OVI). There are seven bits, so the value can be set between 0 and 127.
Tables 5.6 and 5.7 show the relationship between on-chip peripheral module interrupts and
interrupt vector number setting registers.
Table 5.6 Interrupt Request Sources and Vector Number Setting Registers (1)
Register
Vector number setting register
WDT
Vector number setting register A
Vector number setting register B
Vector number setting register C
Vector number setting register D
14–8
Interval interrupt (WDT)
Bits
6–0
Compare-match interrupt (BSC)
Receive-error interrupt (SCI) Receive-data-full interrupt (SCI)
Transmit-data-empty interruptTransmit-end interrupt (SCI)
(SCI)
Input-capture interrupt (FRT) Output-compare interrupt (FRT)
Overflow interrupt (FRT) Reserved
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